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1 tm file number 3043.2 HS-82C54RH radiation hardened cmos programmable interval timer the intersil HS-82C54RH is a high performance, radiation hardened cmos version of the industry standard 8254 and is manufactured using a hardened ?ld, self-aligned silicon gate cmos process. it has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 5mhz. six programmable timer modes allow the HS-82C54RH to be used as an event counter, elapsed time indicator, a programmable one-shot, or for any other timing application. the high performance, radiation hardness, and industry standard con?uration of the HS-82C54RH make it compatible with the hs-80c86rh radiation hardened microprocessor. static cmos circuit design insures low operating power. the intersil hardened ?ld cmos process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95713. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp features electrically screened to smd # 5962-95713 qml quali?d per mil-prf-38535 requirements radiation performance - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - transient upset . . . . . . . . . . . . . . . . . . . . >10 8 rad(si)/s - latch up free epi-cmos low power consumption - iddsb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 a - iddop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ma pin compatible with nmos 8254 and the intersil 82c54 high speed, ?o wait state?operation with 5mhz hs-80c86rh three independent 16-bit counters six programmable counter modes binary or bcd counting status read back command hardened field, self-aligned, junction isolated cmos process single 5v supply military temperature range . . . . . . . . . . . -55 o c to 125 o c ordering information ordering number internal mkt. number temp. range ( o c) 5962r9571301qjc hs1-82c54rh-8 -55 to 125 5962r9571301qxc hs9-82c54rh-8 -55 to 125 5962r9571301vjc hs1-82c54rh-q -55 to 125 data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 pinouts 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view 1 2 3 4 5 6 7 8 9 10 11 12 d7 d6 d5 d4 d3 d2 d1 d0 clk 0 out 0 gate 0 gnd 16 17 18 19 20 21 22 23 24 15 14 13 vdd rd cs a1 a0 out 2 clk 1 ga te 1 out 1 wr clk 2 gate 2 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 gnd d7 d6 d5 d4 d3 d2 d1 d0 clk 0 out 0 gate 0 vdd out1 ga te 1 clk 1 gate 2 out 2 wr rd cs a1 clk 2 a0 pin descriptions symbol pin number type description d7-d0 1-8 i/o data: bi-directional three state data bus lines, connected to system data bus. clk 0 9 i clock 0: clock input of counter 0. out 0 10 o out 0: output of counter 0. gate 0 11 i gate 0: gate input of counter 0. gnd 12 ground: power supply connection. out 1 13 o out 1: output of counter 1. gate 1 14 i gate 1: gate input of counter 1. clk 1 15 i clock 1: clock input of counter 1. gate 2 16 i gate 2: gate input of counter 2. out 2 17 o out 2: output of counter 2. clk 2 18 i clock 2: clock input of counter 2. a0, a1 19-20 i address: select inputs for one of the three counters or control word register for read/write operations. normally connected to the system address bus. a1 a0 selects 0 0 counter 0 0 1 counter 1 1 0 counter 2 1 1 control word register cs 21 i chip select: a low on this input enables the HS-82C54RH to respond to rd and wr signals. rd and wr are ignored otherwise. rd 22 i read: this input is low during cpu read operations. wr 23 i write: this input is low during cpu write operations. vdd 24 vdd: the +5v power supply pin. a 0.1 f capacitor between pins 12 and 24 is recommended for decoupling. HS-82C54RH
3 functional diagram ac test circuits note: includes stray and jig capacitance. ac testing input, output waveform note: ac testing: all input signals must switch between vil -0.4v and vih +0.4v. input rise and fall times are driven at 1ns/v. (8) data bus buffer read/ write logic control word register d7-d0 rd wr a0 a1 cs internal bus counter 1 counter 0 counter 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 out 2 gate 2 clk 2 control word register status latch status register control logic out n gate n clk n crm crl olm oll ce internal bus test condition definition table test condition v1 r1 r2 c1 1 1.7v 510 open 150pf test point output from device under test v1 r1 r2 c1 (note) 1.5v 1.5v vil -0.4v input vih +0.4v vol input voh HS-82C54RH
4 waveforms figure 1. write figure 2. read figure 3. recovery figure 4. clock and gate twhax a0-1 data twhdx twlwh tdvwh tavwl valid wr cs tslwl bus trhdz valid trhax tslrl trldv a0-1 cs data rd trlrh tavrl bus rd, wr trhrl twhwl tchgx tch1ch2 tgvch tglov tglgh tclov tghgl tchgx tgvch tcl1cl2 tclcl tclch tchcl clk gate g output 0 HS-82C54RH
5 burn-in circuits static configuration for both flatpack and sbdip package notes: 1. vdd = 6.5v 5% 2. t a = 125 o c minimum 3. resistors = 10k ? 4. idd < 100 a 5. ac: f0 is compliment of f0 f0 is a 50% duty cycle pulse burst f0 is left high after pulse burst dynamic configuration for both flatpack and sbdip package notes: 6. vdd = 6.5v 5% (burn-in) 7. vdd = 6.0v 5% (life test) 8. t a = 125 o c minimum 9. idd < 20ma 10. resistors = 10k ?, except for loads = 2.7k ? 11. -0.3v vil 0.8v 12. vdd -1.0v vih vdd +0.5v 13. ac: f0 is compliment of f0 f0 = 100khz 10%, 50% duty cycle f1 = f0/2, f2 = f1/2 . . . f10 = f9/2 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 24 15 14 13 23 vdd open f0 open open f0 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 24 15 14 13 23 vdd load f2 load load f9 f7 f6 f5 f4 f3 f8 f10 f11 f1 f0 f0 vdd load 2.7k ? 2.7k ? irradiation circuits HS-82C54RH notes: 14. vdd = 5.5v 10%, t a = 25 o c 15. group e testing is performed in sidebrazed dip 16. group e sample size is 2 die/wafer 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 n/c n/c 5.5v n/c 5.5v HS-82C54RH
6 functional description general the HS-82C54RH is a programmable interval timer/counter designed for use with microcomputer systems. it is a general purpose, multi-timing element that can be treated as an array of i/o ports in the system software. the HS-82C54RH solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. instead of setting up timing loops in software, the programmer con?ures the HS-82C54RH to match his requirements and programs one of the counters for the desired delay. after the desired delay, the HS-82C54RH will interrupt the cpu. software overhead is minimal and variable length delays can easily be accommodated. some of the other timer functions common to micro- computers which can be implemented with the HS-82C54RH are: real time clock event counter digital one-shot programmable rate generator square wave generator binary rate multiplier complex waveform generator complex motor controller data bus buffer this three-state, bi-directional, 8-bit buffer is used to interface the HS-82C54RH to the system bus (see figure 5). read/write logic the read/write logic accepts inputs from the system bus and generates control signals for the other functional blocks of the HS-82C54RH. a1 and a0 select one of the three counters or the control word register to be read from/written into. a ?ow?on the rd input tells the HS-82C54RH that the cpu is reading one of the counters. a ?ow on the wr input tells the HS-82C54RH that the cpu is writing either a control word or an initial count. both rd and wr are quali?d by cs; rd and wr are ignored unless the HS-82C54RH has been selected by holding cs low. control word register the control word register (figure 6) is selected by the read/write logic when a1, a0 = 11. if the cpu then does a write operation to the HS-82C54RH, the data is stored in the control word register and is interpreted as a control word used to de?e the counter operation. the control word register can only be written to; status information is available with the read-back command. counter 0, counter 1, counter 2 these three functional clocks are identical in operation, so only a single counter will be described. the internal block diagram of a single counter is shown in figure 7. the counters are fully independent. each counter may operate in a different mode. the control word register is shown in the ?ure; it is not part of the counter itself, but its contents determine how the counter operates. (8) control word register d7-d0 rd wr a0 a1 cs internal bus counter 1 counter 0 counter 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 out 2 gate 2 clk 2 data bus buffer read/ write logic figure 5. data bus buffer and read/write logic function (8) data bus buffer read/ write logic control word register d7-d0 rd wr a0 a1 cs internal bus counter 1 counter 0 counter 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 out 2 gate 2 clk 2 figure 6. control word register and counter functions HS-82C54RH
7 the status register, shown in the ?ure, when latched, contains the current contents of the control word register and status of the output and null count ?g. (see detailed explanation of the read-back command.) the actual counter is labeled ce for ?ounting element? it is a 16-bit presettable synchronous down counter. olm and oll are two 8-bit latches. ol stands for ?utput latch? subscripts m and l for ?ost signi?ant byte?and ?east signi?ant byte? respectively. both are normally referred to as one unit and called just ol. these latches normally ?ollow?the ce, but if a suitable counter latch command is sent to the HS-82C54RH, the ol latches the present count until read by the cpu and then returns to ?ollowing?the ce. one latch at a time is enabled by the counters control logic to drive the internal bus. this is how the 16-bit counter communicates over the 8-bit internal bus. note that the ce itself cannot be read; whenever you read the count, it is the ol that is being read. similarly, there are two 8-bit registers called crm and crl (for ?ount register?. both are normally referred to as one unit and called just cr. when a new count is written to the counter, the count is stored in the cr and later transferred to the ce. the control logic allows one register at a time to be loaded from the internal bus. both bytes are transferred to the ce simultaneously. crm and crl are cleared when the counter is programmed for one byte counts (either most signi?ant byte only or least signi?ant byte only) the other byte will be zero. note that the ce cannot be written into; whenever a count is written, it is written into the cr. the control logic is also shown in the diagram. clkn, gaten, and outn are all connected to the outside world through the control logic. HS-82C54RH system interface the HS-82C54RH is treated by the system software as an array of peripheral i/o ports; three are counters and the fourth is a control word register for mode programming. basically, the select inputs a0, a1 connect to the a0, a1 address bus signals of the cpu. the cs can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder, such as a intersil hd-6440 for larger systems. operational description general after power-up, the state of the HS-82C54RH is undefined. the mode, count value, and output of all counters are undefined. how each counter operates is determined when it is programmed. each counter must be programmed before it can be used. unused counters need not be programmed. programming the HS-82C54RH counters are programmed by writing a control word and then an initial count. all control words are written into the control word register, which is selected when a1, a0 = 11. the control word speci?s which counter is being programmed. by contrast, initial counts are written into the counters, not the control word register. the a1, a0 inputs are used to select the counter to be written into. the format of the initial count is determined by the control word used. write operations the programming procedure for the HS-82C54RH is very ?xible. only two conventions need to be remembered: 1. for each counter, the control word must be written before the initial count is written. 2. the initial count must follow the count format speci?d in the control word (least signi?ant byte only, most control word register status latch status register control logic out n gate n clk n crm crl olm oll ce internal bus figure 7. counter internal block diagram data bus (8) address bus (16) control bus a1 a0 i/or i/o w 8 cs a1 a0 counter 0 out gate clk counter 1 out gate clk counter 2 out gate clk d0-d7 rd wr HS-82C54RH figure 8. HS-82C54RH system interface HS-82C54RH
8 significant byte only, or least signi?ant byte and then most signi?ant byte). since the control word register and the three counter shave separate addresses (selected by the a1, a0 inputs), and each control word speci?s the counter it applies to (sc0, sc1 bits), no special instruction sequence is required. any programming sequence that follows the conventions above is acceptable. control word format a1, a0 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 sc1 sc2 rw1 rw0 m2 m1 m0 bcd sc - select counter: m - mode: sc1 sc0 m2 m1 m0 0 0 select counter 0 0 0 0 mode 0 0 1 select counter 1 0 0 1 mode 1 1 0 select counter 2 x 1 0 mode 2 1 1 read-back command (see read operations) x 1 1 mode 3 rw - read/write 1 0 0 mode 4 rw1 rw0 1 0 1 mode 5 0 0 counter latch command (see read operations) bcd - binary coded decimal: 0 1 read/write least significant byte only. 0 binary counter 16-bits 1 0 read/write most significant byte only. 1 binary coded decimal (bcd) counter (4 decades) 1 1 read/write least significant byte first, then most significant byte. note: don? care bits (x) should be 0 to insure compatibility with future products. figure 9. control word format a1 a0 a1 a0 control word - counter 0 1 1 control word - counter 2 1 1 lsb of count - counter 0 0 0 control word - counter 1 1 1 msb of count - counter 0 0 0 control word - counter 0 1 1 control word - counter 1 1 1 lsb of count - counter 2 1 0 lsb of count - counter 1 0 1 msb of count - counter 2 1 0 msb of count - counter 1 0 1 lsb of count - counter 1 0 1 control word - counter 2 1 1 msb of count - counter 1 0 1 lsb of count - counter 2 1 0 lsb of count - counter 0 0 0 msb of count - counter 2 1 0 msb of count - counter 0 0 0 a1 a0 a1 a0 control word - counter 0 1 1 control word - counter 1 1 1 control word - counter 1 1 1 control word - counter 0 1 1 control word - counter 2 1 1 lsb of count - counter 1 0 1 lsb of count - counter 2 1 0 control word - counter 2 1 1 lsb of count - counter 1 0 1 lsb of count - counter 0 0 0 lsb of count - counter 0 0 0 msb of count - counter 1 0 1 msb of count - counter 0 0 0 lsb of count - counter 2 1 0 msb of count - counter 1 0 1 msb of count - counter 0 0 0 msb of count - counter 2 1 0 msb of count - counter 2 1 0 note: in all four examples, all counters are programmed to read/write two-byte counts. these are only four of many possible prog ramming sequences. figure 10. a few possible programming sequences HS-82C54RH
9 a new initial count may be written to a counter at any time without affecting the counters programmed mode in anyway. counting will be affected as described in the mode de?itions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the ?st and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. read operations it is often desirable to read the value of a counter without disturbing the count in progress. this is easily done in the HS-82C54RH. there are three possible methods for reading the counters. the ?st is through the read-back command, which is explained later. the second is a simple read operation of the counter, which is selected with the a1, a0 inputs. the only requirement is that the clk input of the selected counter must be inhibited by using either the gate input or external logic. otherwise, the count may be in process of changing when it is read, giving an unde?ed result. counter latch command the other method for reading the counters involves a special software command called the ?ounter latch command? like a control word, this command is written to the control word register, which is selected when a1, a0 = 11. also, like a control word, the sc0, sc1 bits select one of the three counters, but two other bits, d5 and d4, distinguish this command from a control word. a1, a0 = 11; cs = 0; rd = 1; wr = 0 the selected counters output latch (ol) latches the count when the counter latch command is received. this count is held in the latch until it is read by the cpu (or until the counter is reprogrammed). the count is then unlatched automatically and the ol returns to ?ollowing?the counting element (ce). this allows reading the contents of the counters ?n the ??without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. each latched counters ol holds its count until read. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the ?st counter latch command was issued. with either method, the count must be read according to the programmed format; speci?ally, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other; read or write or programming operations of other counters may be inserted between them. another feature of the HS-82C54RH is that reads and writes of the same counter may be interleaved; for example, if the counter is programmed for two byte counts, the following sequence is valid. 1. read least signi?ant byte. 2. write new least signi?ant byte. 3. read most signi?ant byte. 4. write new most signi?ant byte. if a counter is programmed to read or write two-byte counts, the following precaution applies: a program must not transfer control between reading the ?st and second byte to another routine which also reads from that same counter. otherwise, an incorrect count will be read. read-back command the read-back command allows the user to check the count value, programmed mode, and current state of the out pin and null count ?g of the selected counter(s). the command is written into the control word register and has the format shown in figure 12. the command applies to the counters selected by setting their corresponding bits d3, d2, d1 = 1. a0, a1 = 11; cs = 0; rd = 1; wr = 0 the read-back command may be used to latch multiple counter output latches (ol) by setting the count bit d5 = 0 and selecting the desired counter(s). this single command is functionally equivalent to several counter latch d7 d6 d5 d4 d3 d2 d1 d0 sc1sc00 0xxxx sc1, sc0 - specify counter to be latched sc1 sc1 counter 00 0 00 1 11 2 1 1 read-back command d5, d4 = 00 designates counter latch command x = don? care note: don? care bits (x) should be 0 to insure compatibility with future products. figure 11. counter latch command format d7 d6 d5 d4 d3 d2 d1 d0 11 count st a tus cnt 2 cnt 1 cnt 0 0 d5: 0 = latch count of selected counters(s) d4: 0 = latch status of selected counters(s) d3: 1 = select counter 2 d2: 1 = select counter 1 d1: 1 = select counter 0 d0: reserved for future expansion; must be 0 figure 12. read-back command format HS-82C54RH
10 commands, one for each counter latched. each counters latched count is held until it is read (or the counter is reprogrammed). that counter is automatically unlatched when read, but other counters remain latched until they are read. if multiple count read-back commands are issued to the same counter without reading the count, all but the ?st are ignored; i.e., the count which will be read is the count at the time the ?st read-back command was issued. the read-back command may also be used to latch status information of selected counter(s) by setting status bit d4 = 0. status must be latched to be read; status of a counter is accessed by a read from that counter. the counter status format is shown in figure 13. bits d5 through d0 contain the counters programmed mode exactly as written in the last mode control word. output bit d7 contains the current state of the out pin. this allows the user to monitor the counters output via software, possibly eliminating some hardware from a system. null count bit d6 indicates when the last count written to the counter register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the mode of the counter and is described in the mode de?itions, but until the count is loaded into the counting element (ce), it can? be read from the counter. if the count is latched or read before this time, the count value will not re?ct the new count just written. the operation of null count is shown in figure 14. if multiple status latch operations of the counter(s) are performed without reading the status, all but the ?st are ignored; i.e., the status that will be read is the status of the counter at the time the ?st status read-back command was issued. both count and status of the selected counter(s) may be latched simultaneously by setting both count and status bits d5, d4 = 0. this is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also. speci?ally, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the ?st are ignored. this is illustrated in figure 15. if both count and status of a counter are latched, the ?st read operation of that counter will return latched status, regardless of which was latched ?st. the next one or two reads (depending on whether the counter is programmed for one or two byte counts) return latched count. subsequent reads return unlatched count. d7 d6 d5 d4 d3 d2 d1 d0 out put null count rw1 rw0 m2 m1 m0 bcd d7 1 = out pin is 1 0 = out pin is 0 d6 1 = null count 0 = count available for reading d5-d0 = counter programmed mode (see figure 5) figure 13. status byte this action: causes: a. write to the control word register: (note 17) null count = 1 b. write to the count register (cr): (note 18) null count = 1 c. new count is loaded into ce (cr ce): null count = 0 notes: 17. only the counter specified by the control word will have its null count set to 1. null count bits of other counters are unaffected. 18. if the counter is programmed for two-byte counts (least significant byte then most significant byte) null count goes to 1 when the second byte is written. figure 14. null count operation command description result d7 d6 d5 d4 d3 d2 d1 d0 11000010 read back count and status of counter 0 count and status latched for counter 0 11100100 read-back status of counter 1 status latched for counter 1 11101100 read-back status of counters 2, 1 status latched for counter 2, but not counter 1 11011000 read-back count of counter 2 count latched for counter 2 11000100 read-back count and status of counter 1 count latched for counter 1, but not status 11100100 read-back status of counter 1 command ignored, status already latched for counter 1 figure 15. read-back command example HS-82C54RH
11 mode de?itions the following are de?ed for use in describing the operation of the HS-82C54RH. clk pulse: a rising edge, then a falling edge, in that order, of a counters clk input. trigger: a rising edge of a counters gate input. counter loading: the transfer of a count from the cr to the ce (see ?unctional description? mode 0: interrupt on terminal count mode 0 is typically used for event counting. after the control word is written, out is initially low, and will remain low until the counter reaches zero. out then goes high and remains high until a new count or a new mode 0 control word is written to the counter. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after the control word and initial count are written to a counter, the initial count will be loaded on the next clk pulse. this clk pulse does not decrement the count, so for an initial count of n, out does not go high until n + 1 clk pulses after the initial count is written. if a new count is written to the counter it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: 1. writing the ?st byte disables counting. out is set low immediately (no clock pulse required). 2. writing the second byte allows the new count to be loaded on next clk pulse. this allows the counting sequence to be synchronized by software. again out does not go high until n + 1 clk pulses after the new count of n is written. if an initial count is written while gate = 0, it will still beloaded on the next clk pulse. when gate goes high, out will go high n clk pulses later; no clk pulse is needed to load the counter as this has already been done. notes: 19. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 20. the counter is always selected ( cs always low). 21. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 22. lsb stands for ?east significant byte?of count. 23. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 24. n stands for an undefined count. 25. vertical lines show transitions between count values. figure 17. mode 0 mode 1: hardware retriggerable one-shot out will be initially high. out will go low on the clk pulse following a trigger to begin the one-shot pulse, and will remain low until the counter reaches zero. out will then go high and remain high until the clk pulse after the next trigger. after writing the control word and initial count, the counter is armed. a trigger results in loading the counter and setting cs rd wr a1 a0 01000 write into counter 0 01001 write into counter 1 01010 write into counter 2 01011 write control word 00100 read from counter 0 00101 read from counter 1 00110 read from counter 2 00111 no-operation (three-state) 1xxxx no-operation (three-state) 0 1 1 x x no-operation (three-state) figure 16. read/write operations summary nnnn 00 00ff ff 0 1 2 3 cw = 10 lsb = 4 wr clk gate out nnnn 00000 0 1 2 2 2 cw = 12 lsb = 3 wr clk gate out nnnn 00 0 2 1 2 cw = 10 lsb = 3 wr clk gate out lsb = 2 0 4 ff fe 0 3 ff ff ff ff 0 1 0 0 0 3 HS-82C54RH
12 out low on the next clk pulse, thus starting the one-shot pulse n clk cycles in duration. the one-shot is retriggerable, hence out will remain low for n clk pulses after any trigger. the one-shot pulse can be repeated without rewriting the same count into the counter. gate has no effect on out. if a new count is written to the counter during a one-shot pulse, the current one-shot is not affected unless the counter is retriggered. in that case, the counter is loaded with the new count and the one-shot pulse continues until the new count expires. notes: 26. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 27. the counter is always selected ( cs always low). 28. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 29. lsb stands for ?east significant byte?of count. 30. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 31. n stands for an undefined count. 32. vertical lines show transitions between count values. figure 18. mode 1 mode 2: rate generator this mode functions like a divide-by-n counter. it is typically used to generate a real time clock interrupt. out will initially be high. when the initial count has decremented to 1, out goes low for one clk pulse. out then goes high again, the counter reloads the initial count and the process is repeated. mode 2 is periodic; the same sequence is repeated inde?itely. for an initial count of n, the sequence repeats every n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low during an output pulse, out is set high immediately. a trigger reloads the counter with the initial count on the next clk pulse; out goes low n clk pulses after the trigger. thus the gate input can be used to synchronize the counter. after writing a control word and initial count, the counter will be loaded on the next clk pulse. out goes low n clk pulses after the initial count is written. this allows the counter to be synchronized by software also. writing a new count while counting does not affect the current counting sequence. if a trigger is received after writing a new count but before the end of the current period, the counter will be loaded with the new count on the next clk pulse and counting will continue from the new count. otherwise, the new count will be loaded at the end of the current counting cycle. notes: 33. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 34. the counter is always selected ( cs always low). 35. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 36. lsb stands for ?east significant byte?of count. wr clk gate out wr clk gate out wr clk gate out cw = 12 lsb = 3 cw = 12 lsb = 3 cw = 12 lsb = 2 lsb = 4 nnnnn 00 00ff0 0 2 3 ff 0 1 2 3 nnnnn 00 0 0 00 0 0 1 2 3 1 2 3 nnnnn 00 0ffff0 0 3 4 fe ff 0 1 2 nnnn 00 00 2 3 1 2 cw = 14 lsb = 3 wr clk gate out nnnn 00 0 0 0 1 2 3 2 2 cw = 12 lsb = 3 wr clk gate out nnnn 00 0 1 2 3 cw = 14 lsb = 4 wr clk gate out lsb = 5 0 3 0 3 0 5 0 4 0 4 0 1 0 3 0 3 0 3 HS-82C54RH
13 37. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 38. n stands for an undefined count. 39. vertical lines show transitions between count values. figure 19. mode 2 mode 3: square wave mode mode 3 is typically used for baud rate generation. mode 3 is similar to mode 2 except for the duty cycle of out. out will initially be high. when half the initial count has expired, out goes low for the remainder of the count. mode 3 is periodic; the sequence above is repeated inde?itely. an initial count of n results in a square wave with a period of n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low while out is low, out is set high immediately; no clk pulse is required. a trigger reloads the counter with the initial count on the next clk pulse. thus the gate input can be used to synchronize the counter.after writing a control word and initial count, the counter will be loaded on the next clk pulse. this allows the counter to be synchronized by software also. writing a new count while counting does not affect the current counting sequence. if a trigger is received after writing a new count but before the end of the current half- cycle of the square wave, the counter will be loaded with the new count on the next clk pulse and counting will continue from the new count. otherwise, the new count will be loaded at the end of the current half-cycle. mode 3 is implemented as follows: even counts: out is initially high. the initial count is loaded on one clk pulse and then is decremented by two on succeeding clk pulses. when the count expires, out changes value and the counter is reloaded with the initial count. the above process is repeated inde?itely. odd counts: out is initially high. the initial count is loaded on one clk pulse, decremented by one on the next clk pulse, and then decremented by two on succeeding clk pulses. when the count expires, out goes low and the counter is reloaded with the initial count. the count is decremented by three on the next clk pulse, and then by two on succeeding clk pulses.when the count expires, out goes high again and the counter is reloaded with the initial count. the above process is repeated inde?itely. so for odd counts, out will be high for (n + 1)/2 counts and low for (n-1)/2 counts. mode 4: software triggered mode out will be initially high. when the initial count expires, out will go low for one clk pulse then go high again.the counting sequence is ?riggered?by writing the initial count. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after writing a control word and initial count, the counter will be loaded on the next clk pulse. this clk pulse does not decrement the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after the initial count is written. if a new count is written during counting, it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: 1. writing the ?st byte has no effect on counting. 2. writing the second byte allows the new count to be loaded on the next clk pulse. this allows the sequence to be ?etriggered?by software. out strobes low n + 1 clk pulses after the new count of n is written. mode 5: hardware triggered strobe (retriggerable) out will initially be high. counting is triggered by a rising edge of gate. when the initial count has expired, out will go low for one clk pulse and then go high again. after writing the control word and initial count, the counter will not be loaded until the clk pulse after a trigger. this clk pulse does not decrement the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after trigger. a trigger results in the counter being loaded with the initial count on the next clk pulse. this allows the counting sequence to be regretted. out strobes low n + 1 clk pulses after any new trigger. gate has no effect on the state of out. if a new count is written during counting, the current counting sequence will not be affected. if a trigger occurs after the new count is written but before the current count expires, the counter will be loaded with the new count on the next clk pulse and counting will continue from there. HS-82C54RH
14 notes: 40. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 41. the counter is always selected ( cs always low). 42. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 43. lsb stands for ?east significant byte?of count. 44. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 45. n stands for an undefined count. 46. vertical lines show transitions between count values. figure 20. mode 3 notes: 47. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 48. the counter is always selected ( cs always low). 49. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 50. lsb stands for ?east significant byte?of count. 51. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 52. n stands for an undefined count. 53. vertical lines show transitions between count values. figure 21. mode 4 nnnn 00 00 0 0 2 4 2 5 2 4 00 2 5 0 5 0 5 nnnn 00 00 0 0 2 4 4 2 4 2 cw = 16 lsb = 4 wr clk gate out cw = 16 lsb = 5 wr clk gate out cw = 16 lsb = 4 wr clk gate out 00 2 4 0 4 0 2 nnnn 00 00 0 0 2 4 2 2 4 2 00 2 4 0 4 0 2 cw = 18 lsb = 3 wr clk gate out cw = 18 lsb = 3 wr clk gate out cw = 18 lsb = 3 wr clk gate out lsb = 2 nnnn 00 0fe ff 0 1 2 0 3 ff fe ff fd nnnn 00 0 0 0 0 1 2 3 3 0 3 ff ff nnnn 00 0 2 1 2 0 1 0 0 0 3 ff ff HS-82C54RH
15 notes: 54. counters are programmed for binary (not bcd) counting and for reading/writing least significant byte (lsb) only. 55. the counter is always selected ( cs always low). 56. cw stands for ?ontrol word? cw = 10 means a control word of 10, hex is written to the counter. 57. lsb stands for ?east significant byte?of count. 58. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most significant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 59. n stands for an undefined count. 60. vertical lines show transitions between count values. figure 22. mode 5 operation common to all modes programming when a control word is written to a counter, all control logic is immediately reset and out goes to a known initial state; no clk pulses are required for this. gate the gate input is always sampled on the rising edge of clk. in modes 0, 2, 3 and 4 the gate input is level sensitive, and logic level is sampled on the rising edge of clk. in modes 1, 2, 3 and 5 the gate input is rising-edge sensitive. in these modes, a rising edge of gate (trigger) sets an edge-sensitive flip-flop in the counter. this flip-flop is then sampled on the next rising edge of clk. the flip-flop is reset immediately after it is sampled. in this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of clk. note that in modes 2 and 3, the gate input is both edge-and level-sensitive. counter new counts are loaded and counters are decremented on the falling edge of clk. the largest possible initial count is 0; this is equivalent to 2 16 for binary counting and 10 4 for bcd counting. the counter does not stop when it reaches zero. in modes 0, 1, 4 and 5 the counter ?raps around?to the highest count, either ffff hex for binary counting or 9999 for bcd counting, and continues counting. modes 2 and 3 are periodic; the counter reloads itself with the initial count and continues counting from there. wr clk gate out wr clk gate out wr clk gate out nnnn 00 00 0 3 0 1 2 3 ff ff n nnnn 000 00 0 1 3 2 3 ff ff 0 2 nn nnnn 0000 ff0 5 fe 0 1 2 3 0 4 ff ff n cw = 1a lsb = 3 cw = 1a lsb = 3 cw = 1a lsb = 3 lsb = 5 minimum and maximum initial counts mode min count max count 010 110 220 320 410 510 note: 0 is equivalent to 2 16 for binary counting and 10 4 for bcd counting. gate pin operations summary signal status modes low or going low rising high 0 disables counting - enables counting 1 - 1) initiates counting 2) resets output after next clock - 2 1) disables counting 2) sets output immediately high initiates counting enables counting 3 1) disables counting 2) sets output immediately high initiates counting enables counting 4 1) disables counting - enables counting 5 - initiates counting - HS-82C54RH
16 die characteristics die dimensions: 4700 m x 5510 m x 485 m 25.4 m interface materials: glassivation: type: sio2 thickness: 8k ? 1k ? top metallization: type: al/si thickness: 11k ? 2k ? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: 7.9 x 10 4 a/cm 2 metallization mask layout HS-82C54RH (3) d5 (2) d6 (1) d7 (24) vdd (23) wr (22) rd (21) cs (20) a1 (19) a0 (18) clk 2 (17) out 2 (16) gate 2 out 0 (10) gate 0 (11) vss (12) out 1 (13) gate 1 (14) d4 (4) d3 (5) d2 (6) d1 (7) d0 (8) clk 0 (9) clk 1 (15) HS-82C54RH
17 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 HS-82C54RH

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